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tc554001af/aft/atr-70v,-85v,-10v 2001-08-16 1/13 toshiba mos digital integrated circuit silicon gate cmos 524,288-word by 8-bit static ram description the tc554001af/aft/atr is a 4,194,304-bit static random access memory (sram) organized as 524,288 words by 8 bits. fabricated using toshiba's cmos silicon gate process technology, this device operates from a single 2.7 to 5.5 v power supply. advanced circuit technology provides both high speed and low power at an operating current of 10 ma/mhz (typ) and a minimum cycle time of 70 ns. it is automatically placed in low-power mode at 2 a standby current (typ) when chip enable ( ce ) is asserted high. there are two control inputs. ce is used to select the device and for data retention control, and output enable ( oe ) provides fast memory access. this device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. the tc554001af/aft/atr is available in a standard plastic 32-pin small-outline package (sop) and normal and reverse pinout plastic 32-pin thin-small-outline package (tsop). features ? low-power dissipation operating: 55 mw/mhz (typical) ? standby current of 5 a (maximum) at ta = 25c ? single power supply voltage of 2.7 to 5.5 v ? power down features using ce . ? data retention supply voltage of 2.0 to 5.5 v ? direct ttl compatibility for all inputs and outputs pin assignment (top view) pin names 32 pin sop & tsop 32 pin tsop a0~a18 address inputs r/w read/write control oe output enable ce chip enable i/o1~i/o8 data inputs/outputs v dd power ( + 5 v) gnd ground 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 v dd a15 a17 r/w a13 a8 a9 a11 a10 i/o8 i/o7 i/o6 i/o5 i/o4 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 gnd ce oe (af/aft) v dd a15 a17 r/w a13 a8 a9 a11 a10 i/o8 i/o7 i/o6 i/o5 i/o4 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 gnd (atr) ce oe ? access times (maximum): 5 v 10% 2.7 v~5.5 v -70v -85v -10v -70v -85v/-10v access time 70 ns 85 ns 100 ns 120 ns 150 ns ce access time 70 ns 85 ns 100 ns 120 ns 150 ns oe access time 35 ns 45 ns 50 ns 70 ns 75 ns ? package: sop32-p-525-1.27 (af) (weight: 1.14 g typ) tsop ii32-p-400-1.27 (aft) (weight: 0.53 g typ) tsop ii32-p-400-1.27a (atr) (weight: 0.53 g typ)
tc554001af/aft/atr-70v,-85v,-10v 2001-08-16 2/13 block diagram operating mode mode ce oe r/w i/o1~i/o8 power read l l h output i ddo write l * l input i ddo output deselect l h h high-z i ddo standby h * * high-z i dds * = don't care h = logic high l = logic low maximum ratings symbol rating value unit v dd power supply voltage ? 0.3~7.0 v v in input voltage ? 0.3 * ~7.0 v v i/o input/output voltage ? 0.5~v dd + 0.5 v p d power dissipation 0.6 w t solder soldering temperature (10s) 260 c t stg storage temperature ? 55~150 c t opr operating temperature 0~70 c * : ? 3.0 v when measured at a pulse width of 50ns column address buffer a1 i/o1 memory cell array 2,048 256 8 (4,194,304) column address decoder column adderss register sense amp ce a2 a3 a4 a5 a7 a6 a12 a14 ce v dd gnd ce r/w oe a0 ce a18 a10 a8 a9 a17 a11a13a15a16 row address decoder row address buffer row address register i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 data control clock generator 8
tc554001af/aft/atr-70v,-85v,-10v 2001-08-16 3/13 dc recommended operating conditions (ta = = = = 0 to 70c) 5 v 10% 2.7 v~5.5 v symbol parameter min typ max min typ max unit v dd power supply voltage 4.5 5.0 5.5 2.7 5.0 5.5 v v ih input high voltage 2.2 ? v dd + 0.3 v dd ? 0.2 ? v dd + 0.3 v v il input low voltage ? 0.3 * ? 0.8 ? 0.3 * ? 0.2 v v dh data retention supply voltage 2.0 ? 5.5 2.0 ? 5.5 v * : ? 3.0v when measured at a pulse width of 50 ns dc characteristics (ta = = = = 0 to 70c, v dd = = = = 5 v 10%) symbol parameter test condition min typ max unit i il input leakage current v in = 0 v~v dd ? ? 1.0 a i lo output leakage current ce = v ih or r/w = v il or oe = v ih , v out = 0 v~v dd ? ? 1.0 a i oh output high current v oh = 2.4 v ? 1.0 ? ? ma i ol output low current v ol = 0.4 v 2.1 ? ? ma t cycle = min ? ? 70 l ddo1 ce = v il and r/w = v ih , i out = 0 ma, other input = v ih /v il t cycle = 1 s ? 15 ? ma t cycle = min ? ? 60 l ddo2 operating current ce = 0.2 v and r/w = v dd ? 0.2 v, i out = 0 ma, other input = v dd ? 0.2 v/0.2 v t cycle = 1 s ? 10 ? ma i dds1 ce = v ih ? ? 3 ma ta = 25c ? 2 5 v dd = 2.0 v~5.5 v ta = 0~70c ? ? 50 ta = 25c ? 2 ? ta = 0~40c ? ? 5 i dds2 standby current ce = v dd ? 0.2 v, v dd = 3.0 v ta = 0~70c ? ? 25 a
tc554001af/aft/atr-70v,-85v,-10v 2001-08-16 4/13 dc characteristics (ta = = = = 0 to 70c, v dd = = = = 3.0 v 10%) symbol parameter test condition min typ max unit i il input leakage current v in = 0 v~v dd ? ? 1.0 a i lo output leakage current ce = v ih or r/w = v il or oe = v ih , v out = 0 v~v dd ? ? 1.0 a i oh output high current v oh = v dd ? 0.2 v ? 1.0 ? ? ma i ol output low current v ol = 0.2 v 0.1 ? ? ma t cycle = min ? ? 30 l ddo2 operating current ce = 0.2 v and r/w = v dd ? 0.2 v, i out = 0 ma, other input = v dd ? 0.2 v/0.2 v t cycle = 1 s ? 5 ? ma ta = 25c ? 2 3 v dd = 3.0 0.3 v ta = 0~70c ? ? 28 ta = 25c ? 2 ? ta = 0~40c ? ? 5 i dds2 standby current ce = v dd ? 0.2 v, v dd = 3.0 v ta = 0~70c ? ? 25 a capacitance (ta = = = = 25c, f = = = = 1 mhz) symbol parameter test condition max unit c in input capacitance v in = gnd 10 pf c out output capacitance v out = gnd 10 pf note: this parameter is periodically sampled and is not 100% tested.
tc554001af/aft/atr-70v,-85v,-10v 2001-08-16 5/13 ac characteristics and operating conditions (ta = = = = 0 to 70c, v dd = = = = 5 v 10%) read cycle tc554001af/aft/atr -70v -85v -10v symbol parameter min max min max min max unit t rc read cycle time 70 ? 85 ? 100 ? t acc address access time ? 70 ? 85 ? 100 t co chip enable access time ? 70 ? 85 ? 100 t oe output enable access time ? 35 ? 45 ? 50 t coe chip enable low to output active 10 ? 10 ? 10 ? t oee output enable low to output active 5 ? 5 ? 5 ? t od chip enable high to output high-z ? 25 ? 30 ? 35 t odo output enable high to output high-z ? 25 ? 30 ? 35 t oh output data hold time 10 ? 10 ? 10 ? ns write cycle tc554001af/aft/atr -70v -85v -10v symbol parameter min max min max min max unit t wc write cycle time 70 ? 85 ? 100 ? t wp write pulse width 50 ? 55 ? 60 ? t cw chip enable to end of write 60 ? 70 ? 80 ? t as address setup time 0 ? 0 ? 0 ? t wr write recovery time 0 ? 0 ? 0 ? t odw r/w low to output high-z ? 25 ? 30 ? 35 t oew r/w high to output active 5 ? 5 ? 5 ? t ds data setup time 30 ? 35 ? 40 ? t dh data hold time 0 ? 0 ? 0 ? ns ac test conditions parameter test condition output load 100 pf + 1 ttl gate input pulse level 0.6 v, 2.4 v timing measurements 1.5 v reference level 1.5 v t r , t f 5 ns
tc554001af/aft/atr-70v,-85v,-10v 2001-08-16 6/13 ac characteristics and operating conditions (ta = = = = 0 to 70c, v dd = = = = 2.7 v to 5.5 v) read cycle tc554001af/aft/atr -70v -85v/-10v symbol parameter min max min max unit t rc read cycle time 120 ? 150 ? t acc address access time ? 120 ? 150 t co chip enable access time ? 120 ? 150 t oe output enable access time ? 70 ? 75 t coe chip enable low to output active 10 ? 10 ? t oee output enable low to output active 5 ? 5 ? t od chip enable high to output high-z ? 50 ? 50 t odo output enable high to output high-z ? 50 ? 50 t oh output data hold time 10 ? 10 ? ns write cycle tc554001af/aft/atr -70v -85v/-10v symbol parameter min max min max unit t wc write cycle time 120 ? 150 ? t wp write pulse width 80 ? 100 ? t cw chip enable to end of write 100 ? 120 ? t as address setup time 0 ? 0 ? t wr write recovery time 0 ? 0 ? t odw r/w low to output high-z ? 50 ? 50 t oew r/w high to output active 5 ? 5 ? t ds data setup time 50 ? 60 ? t dh data hold time 0 ? 0 ? ns ac test conditions parameter test condition output load 100 pf (include jig) input pulse level v dd ? 0.2 v, 0.2 v timing measurements 1.5 v reference level 1.5 v t r , t f 5 ns
tc554001af/aft/atr-70v,-85v,-10v 2001-08-16 7/13 timing diagrams read cycle (see note 1) write cycle 1 (r/w controlled) (see note 4) address t rc t acc t oh t co oe d out t od valid data out t oe t oee t coe t odo hi-z hi-z ce address r/w t wc t as t wr t wp ce d out t cw valid data in t odw d in t ds t dh t oew (see note 2) hi-z (see note 5) (see note 3) (see note 5)
tc554001af/aft/atr-70v,-85v,-10v 2001-08-16 8/13 write cycle 2 ( controlled) (see note 4) note: (1) r/w remains high for the read cycle. (2) if ce goes low coincident with or after r/w goes low, the outputs will remain at high impedance. (3) if ce goes high coincident with or before r/w goes high, the outputs will remain at high impedance. (4) if oe is high during the write cycle, the outputs will remain at high impedance. (5) because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. ce address r/w t wc t as t wr t wp ce d out t cw valid data in t odw d in t ds t dh t coe hi-z hi-z (see note 5) (see note 5)
tc554001af/aft/atr-70v,-85v,-10v 2001-08-16 9/13 data retention characteristics (ta = = = = 0 to 70 c) symbol parameter min typ max unit v dh data retention supply voltage 2.0 ? 5.5 v v dh = 3.0 v ? ? 25 * i dds2 standby current v dh = 5.5 v ? ? 50 a t cdr chip deselect to data retention mode time 0 ? ? ns t r recovery time 5 ? ? ms * : 5 a (max) at ta = 0 to 40 c controlled data retention mode note: when ce is operating at the v ih level (2.2v), the standby current is given by i dds1 during the transition of v dd from 4.5 to 2.4v. ce v dd 4.5 v gnd v ih data retention mode t r (see note) (see note) t cdr v dd ? 0.2 v ce
tc554001af/aft/atr-70v,-85v,-10v 2001-08-16 10/13 package dimensions weight: 1.14 g (typ)
tc554001af/aft/atr-70v,-85v,-10v 2001-08-16 11/13 package dimensions weight: 0.53 g (typ)
tc554001af/aft/atr-70v,-85v,-10v 2001-08-16 12/13 package dimensions weight: 0.53 g (typ)
tc554001af/aft/atr-70v,-85v,-10v 2001-08-16 13/13 ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ? handling guide for semiconductor devices, ? or ? toshiba semiconductor reliability handbook ? etc.. ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ( ? unintended usage ? ). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer ? s own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. ? the information contained herein is subject to change without notice. 000707eba restrictions on product use

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